1. Field of the Invention
The present invention relates in general to a method of testing a packaged semiconductor memory array for redundancy implementation and, in particular, to a test circuit for acquiring redundancy information from a packaged memory chip.
2. Description of the Prior Art
There exists a need to identify the locations and extent of redundancy implementation on packaged semiconductor parts such as a memory array. Information such as whether a part has been repaired, whether row or column redundancy has been implemented, and on which address, is useful in the manufacture of semiconductor parts. This redundancy information can be utilized with failure analysis, device debugging, and yield analysis.
In particular, it would be desirable to have the capability of performing multiple tests on packaged parts which would provide information on the redundancy implemented in order to improve production analysis of packaged semiconductor chips ready for shipping. These tests would allow the following questions to be answered: 1) Is the device prime or has it been repaired with redundant elements? 2) Has row redundancy been implemented, and on which row addresses? 3) Has column redundancy been implemented, on which column addresses, and for which output? The present invention provides a method and system for testing a packaged semiconductor part in order to answer these important questions of memory array redundancy implementation.